Abstract:

This paper proposes an energy efficient technique with two-phase clocked adiabatic logic. A simulative investigation on the proposed circuit has been carried out in SPICE at 0.18 μm technology node. Further NAND and NOR gates have been implemented by this technique and hence compared with the standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) logic. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic within 10 to 150MHz transition frequency range. Simulation results obtained from the technique cited just before have strongly ratified its validation & use in low power digital devices operated at low frequency.