Abstract

Barrel shifter is one of the important data path elements and widely used in many key computer operations from address decoding to computer arithmetic, using basic operations like data shifting and rotation. In this paper MUX based barrel shifter circuits are designed and implemented in 0.6μm, N-well CMOS process using three different logic design styles, namely, optimized static CMOS, transmission gate (TG) CMOS and dual rail domino CMOS logic. The proposed barrel shifter architecture implementation shows large reduction in the propagation delay, while keeping the almost similar average power consumption as compared to the implementation by Ramin Rafati [10]. A further inter comparison of implementations using three different logic design styles for various performance and characteristic parameters like circuit delay, average power, maximum instantaneous power, leakage Power, transistor count, layout core area, total routing length and number of via are presented.