LOW-POWER FLOATING BITLINE 8-T SRAM DESIGN WITH WRITE ASSISTANT CIRCUITSadmin glcd
از لینک زیر میتوانید مقاله LOW-POWER FLOATING BITLINE 8-T SRAM DESIGN WITH WRITE ASSISTANT CIRCUITS همراه با فایل شبیه سازی hspice آنرا خریداری کنید .
Low power Static RAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90 nm CMOS technology. It can operate at 1 GHz when Vdd is 1 V and at 143 MHz when Vdd is 0.5 V. Moreover, it consumes around 6.6 mW to 670 uW during access cycles.